1. Technical Field
The disclosure relates to an apparatus. Particularly, the disclosure relates to a measuring apparatus.
2. Description of Related Art
As electronic system products are gradually miniaturized, various devices originally crowded on a circuit board are gradually packaged in a single package structure, and are further integrated to a single chip of heterogeneous integration. Though, during the integration process, a multi-function and heterogeneous single chip structure requires different manufacturing processes in accordance with different materials. However, considerable time and investment have to be spent with respect to such situation. Facing to a current market pattern of short product cycles and low-cost requirements, development of the system integration heterogeneous chip is rather uneconomic. Therefore, to integrate chips of different functions in a same package structure becomes a worthy development direction.
Current techniques for integrating different chips into the same package structure include a system on chip (SoC) technique and a system in package (SiP) technique, etc. In these techniques, a plurality of chips is generally packaged as a package device, in which the chips can be evenly distributed on a substrate, or the chips can be directly stacked. Moreover, another solution is to stack different chips into a whole group of chips according to a bump stacking method (which is usually performed in collaboration with wafer thinning).
In the bump stacking structure, since multiple layers of the chips are stacked through bump bonding, the complexity of the structure is increased. After the chips are stacked through the bump bonding, to observe a thermal stress/strain state of each chip and each bump caused by thermal expansion coefficient differences of different chips, or mechanical stress/strain caused by external force or gravity, new measurement methods have to be developed to effectively and promptly obtain the stress/strain states of the chips, so as to use such real-time information to accelerate design and process improvement to enhance competitiveness.